Imaging devices, including charge coupled devices (CCD) and complementary metal oxide semiconductor (CMOS) sensors have commonly been used in photo-imaging applications.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630 to Rhodes, U.S. Pat. No. 6,376,868 to Rhodes, U.S. Pat. No. 6,310,366 to Rhodes et al., U.S. Pat. No. 6,326,652 to Rhodes, U.S. Pat. No. 6,204,524 to Rhodes, U.S. Pat. No. 6,333,205 to Rhodes, and U.S. Patent Appln. Pub. No. 2002/0117690. The disclosures of each of the forgoing are hereby incorporated by reference in their entirety.
An imager, for example, a CMOS imager includes a focal plane array of pixel cells, each cell includes a photosensor, for example, a photogate, a photoconductor, or a photodiode overlying a substrate for producing a photo-generated charge in a doped region of the substrate. A readout circuit is provided for each pixel cell and includes at least a source follower transistor and a row select transistor for coupling the source follower transistor to a column output line. The pixel cell also typically has a floating diffusion node, connected to the gate of the source follower transistor. Charge generated by the photosensor is sent to the floating diffusion node. The imager may also include a transfer transistor for transferring charge from the photosensor to the floating diffusion node and a reset transistor for resetting the floating diffusion node to a predetermined charge level prior to charge transference.
A conventional pixel cell 10 of an image sensor, such as a CMOS imager, is illustrated in FIG. 1. Pixel cell 10 typically includes a photodiode 12 having a p-region 12a and n-region 12b in a p-substrate 14. The pixel also includes a transfer transistor with associated gate 16, a floating diffusion region 18 formed in a more heavily doped p-type well 20, and a reset transistor with associated gate 22. Photons striking the surface of the p-region 12a of the photodiode 12 generate electrons that are collected in the n-region 12b of the photodiode 12. When the transfer gate 16 is on, the photon-generated electrons in the n-region 12b are transferred to the floating diffusion region 18 as a result of the potential difference existing between the photodiode 12 and floating diffusion region 18. Floating diffusion region 18 is coupled to the gates of a source follower transistor 24, which receives the charge temporarily stored by the floating diffusion region 18 and transfers the charge to a first source/drain terminal of a row select transistor and associated gate 26. When the row select signal RS goes high, the photon-generated charge is transferred to the column line 28 where it is further processed by a sample/hold circuit and signal processing circuits (not shown).
In the operation of the pixel cell 10 illustrated in FIG. 1, the charge accumulated in the photodiode 12 is typically transferred by the transfer transistor gate 16 to the floating diffusion region 18. The transfer transistor gate 16 is activated when the charge accumulated in the photodiode 12 reaches a predetermined level. Once activated, the charge is transferred from the photodiode 12 to the floating diffusion region 18.
One problem associated with the FIG. 1 pixel cell 10 is that the floating diffusion region 18 can absorb charge only up to its saturation level. Once the floating diffusion region 18 has reached its saturation level, it cannot respond any longer to incoming electrons from the photodiode 12. The “surplus” charge in the photodiode 12 that can no longer be transferred to the saturated floating diffusion region 18 is typically transferred to adjacent pixel cells, and their associated charge collection regions. The surplus charge often leads to image lag and “blooming” in adjacent pixel cells. Blooming results from the overflow of charge from one pixel cell to the next and can create a bright spot or streak in a resultant image.
Referring to FIG. 2, one method of increasing the storage capacity of a floating diffusion region 18 of a pixel cell 10 is to form a capacitor 34 (known as an array capacitor) that is electrically connected to the floating diffusion region 18. Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of a CMOS imager having a capacitor connected to the floating diffusion region are described in U.S. Patent Appln. Pub. No. 2002/0117690 to Rhodes. The disclosure of the foregoing is hereby incorporated by reference in its entirety.
Although the addition of the array capacitor 34 increases the capacitance of the floating diffusion region 18, and thereby allows for higher saturation limits, the addition of a capacitor to a pixel cell has its own drawbacks. For example, the capacitor 34 is typically formed at the same time as the periphery capacitors (those formed outside of the pixel cell). The periphery capacitors are part of the sample and hold circuits external to the pixel cell 10 and are used to store the reference (full signal) and the output signal of an associated photodiode 12 of each pixel cell 10. The periphery capacitors are typically formed having a higher capacitance than that which is required for the array capacitor 34 connected to the floating diffusion region 18. Having a high capacitance array capacitor 34 leads to certain problems including image lag and charge transfer inefficiency. Therefore, optimally, the array capacitor 34 in pixel cell 10 should have a capacitance lower than that of the periphery capacitor.
There are, however, several disadvantages associated with reducing the capacitance of array capacitor 34 of pixel cell 10. For example, a conventional method of reducing capacitance includes increasing the thickness of the capacitor's dielectric layer. Increasing the dielectric thickness, however, also decreases capacitance in the periphery capacitors, as the array capacitor (e.g., 34) and the periphery capacitors are formed simultaneously. Therefore, additional process steps must be taken to ensure that the dielectric layer thickness of the periphery capacitors is smaller than that of the array capacitor 34. Such additional process steps are costly and reduce manufacturing throughput potentials.
Another method of decreasing capacitance of array capacitor 34 is by scaling the capacitor 34. By reducing the size of the capacitor 34, the area of the capacitor (and capacitance) will decrease as well. However, the reduction in size increases the overall amount of variation in capacitance from one array capacitor to another array capacitor (e.g., of another pixel cell) due to difficulties in maintaining critical dimension (CD) control during the photolithography process. Therefore, as the physical size of the capacitor is reduced, the percentage of CD error due to photolithography and etch processing increases. As a result, the capacitance in the resulting array capacitor varies greatly, and cannot be formed consistently. Thus, it is desirable to develop an array capacitor for storing additional charge from the floating diffusion region with reduced capacitance as compared with the periphery capacitors. Further, such array capacitors should be easily manufactured with consistent results.